This invention relates to an adder, and more particularly to an adder having a plurality of sub operand stages, for processing operands with widths greater than the width of the sub operand stages.
Various adder concepts have been devised in the past. The following types of adders have been considered in connection with bit slice operation: carry-ripple adders, carry-look ahead adders, carry-by-pass adders, carry-select adders. The function of these adders is disclosed, for example, in U.S. Pat. Nos. 3,993,891 and 3,316,393. Their functioning therefore need not be discussed in greater detail.
The object of the present invention is to specify an adder of the above type whose structure is as regular as possible, whereby the individual adder cells do not differ greatly in the size of their layout.